The present disclosure relates to a semiconductor device having a configuration in which an insulator layer and a semiconductor layer are laminated on a semiconductor substrate, a method of manufacturing the same, and a semiconductor unit including the semiconductor device.
In semiconductor integrated circuits including CMOS (Complementary Metal Oxide Semiconductor) transistors, higher integration and higher operation speed have been studied. Recently, in terms of low power consumption, conversion of volatile memories to nonvolatile memories has been studied, and, for example, MRAMs (Magnetoresistive Random Access Memories) have been developed (for example, refer to Japanese Unexamined Patent Application Publication No. 2010-171166).
Incidentally, a contact electrode connected to a source-drain region of a transistor is typically disposed on a principal surface where the transistor is formed of a substrate; however, recently, an attempt to dispose the contact electrode on a back surface of the substrate has been made. For example, Japanese Unexamined Patent Application Publication No. 2010-171166 discloses that, while a diffusion layer and a silicide layer of a main element are formed on a front surface of a silicon (Si) substrate, a contact electrode is so disposed as to pass through the substrate from a back surface of the substrate. The contact electrode from the back surface passes through the substrate and the diffusion layer to be connected to the silicide layer. Flexibility in a wiring path and the like is enhanced by such a configuration, thereby leading to an advantage in design.